30 lines
420 B
Verilog
30 lines
420 B
Verilog
module counter4bit_2clock(clk0, rst0, clk1, rst1, q0, q1);
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input clk0;
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input rst0;
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output [3:0] q0;
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reg [3:0] q0;
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input clk1;
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input rst1;
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output [3:0] q1;
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reg [3:0] q1;
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always @ (posedge clk0)
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begin
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if(rst0)
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q0 <= 4'b0000;
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else
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q0 <= q0 + 1;
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end
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always @ (posedge clk1)
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begin
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if(rst1)
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q1 <= 4'b0000;
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else
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q1 <= q1 + 1;
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end
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endmodule
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