OpenFPGA/openfpga_flow/openfpga_cell_library/verilog
tangxifan 958ef37a83
Merge pull request #864 from yunuseryilmaz18/master
Update dpram16k.v, dpram_2048x8.v, and dpram1k.v
2022-10-30 12:16:21 -07:00
..
adder.v
aib.v
buf4.v
dff.v [arch] add arch that supports negative edge triggered flip-flop 2022-05-09 16:32:01 +08:00
dpram.v Update dpram.v 2022-10-27 08:29:56 +03:00
dpram1k.v Update dpram1k.v 2022-10-26 16:32:14 +03:00
dpram8k.v
dpram16k.v Update dpram16k.v 2022-10-27 08:28:58 +03:00
dpram_2048x8.v Update dpram_2048x8.v 2022-10-26 16:31:16 +03:00
frac_lut4_arith.v
frac_mem_32k.v Update frac_mem_32k.v 2022-10-20 09:48:29 +03:00
frac_mult_16x16.v [HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block 2021-04-24 14:57:09 -06:00
frac_mult_36x36.v Added new cell library for fracturable dsp36 2022-10-21 17:30:20 +03:00
gpio.v [Test] Update test case by using GPIO with config_done signals 2022-02-24 09:49:34 -08:00
inv.v
latch.v
lut6.v
mult_8x8.v
mult_32x32.v
mult_36x36.v
mux2.v
or2.v
spram_4x1.v
sram.v [HDL] Temporarily disable WLR func in primitive HDL modeling 2021-09-20 17:07:51 -07:00
tap_buf4.v