tangxifan 0c2ad5ab5e critical bug fixed for some corner cases		2019-11-13 20:45:41 -07:00
..
backend_assistant	critical bug fixed for some corner cases	2019-11-13 20:45:41 -07:00
base	now we use module manager to generate analysis SDC, being independent from VPR structures	2019-11-10 21:15:34 -07:00
bitstream	critical bugs fixed for routing module naming; and speed up local wire detection in Verilog writer	2019-11-08 15:01:30 -07:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
module_builder	critical bug fixed for some corner cases	2019-11-13 20:45:41 -07:00
router	fixed bugs in configure pb_rr_graph and dependence on testbenches	2019-08-16 18:20:30 -06:00
shell	added Verilog generation for preconfig top module	2019-10-29 13:54:35 -06:00
spice	Rename SCFF to CCFF, configuration chain flip flop	2019-09-26 11:32:57 -06:00
verilog	critical bug fixed for some corner cases	2019-11-13 20:45:41 -07:00