tangxifan 0b74575606 [Arch] Update arch using global reset tile port		2021-01-09 18:04:55 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Bug fix in the and2_or2 benchmark	2020-09-17 10:35:13 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Updating variable name in ys to call BLIF output file.	2020-12-18 03:18:46 -08:00
openfpga_arch	[Arch] Update arch using global reset tile port	2021-01-09 18:04:55 -07:00
openfpga_cell_library	[HDL] Update dff netlist for SCFF used in configuration chain	2021-01-04 17:17:35 -07:00
openfpga_shell_scripts	Updating write_verilog_testbench by removing option explicit_port_mapping	2020-12-22 22:17:50 -08:00
openfpga_simulation_settings	add example simulation setting for openfpga flow	2020-06-11 19:31:15 -06:00
scripts	[Bugfix] Honors yosys_tmpl parameter in flow script	2020-12-03 12:24:24 -07:00
tasks	[Test] Add test case for the SCFF usage in configuration chain	2021-01-04 17:30:19 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	Adding arch xml from SOFA repo. Also updating the script with its file location	2020-12-16 04:14:18 -08:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00