OpenFPGA/openfpga_flow/benchmarks/quicklogic_tests
Tarachand Pagarani ce76c58422 add shift register test case 2021-03-05 09:06:05 -08:00
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Simon_bit_serial_top_module/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
ULPSH_fabric/rtl/src Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00
bin2bcd Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00
cavlc_top/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
cf_fft_256_8/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
counter Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00
counter120bitx5/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
counter_16bit/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
dct_mac/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
des_perf/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
diffeq_f_systemC/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
i2c_master_top/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
iir/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
io_reg Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00
io_tc1/rtl Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00
jpeg_qnr/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
multi_enc_decx2x4/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
rs_decoder/rtl Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00
rs_decoder_1/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
sdc_controller/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
sha256/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
shift_reg_8192/rtl add shift register test case 2021-03-05 09:06:05 -08:00
simon_bit_serial Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00
unsigned_mult_80/rtl Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00