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OpenFPGA/openfpga_flow/benchmarks/quicklogic_tests/shift_reg_8192/rtl
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Tarachand Pagarani ce76c58422 add shift register test case 2021-03-05 09:06:05 -08:00
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shift_reg_8192.v add shift register test case 2021-03-05 09:06:05 -08:00