riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial
History
Lalit Sharma 44a979288b Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00
..
rtl Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00
testbench Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00
README.txt Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00

README.txt

This file contains invisible Unicode characters

This file contains invisible Unicode characters that are indistinguishable to humans but may be processed differently by a computer. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.

Disclaimer:
The use of this code is at your own risk. Of course, we do made every effort to ensure 
that the reference files are free of bugs and issues. We also tested the design on FPGAs 
to make sure that it actually works.