AurelienUoU b4c97f86a3 Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches		2019-05-21 17:24:06 -06:00
..
fpga_spice_bench.txt	Add MCNC Benchmarks netlists generation to travis regression test	2019-05-17 15:22:04 -06:00
mcnc_benchmark.txt	Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches	2019-05-21 17:24:06 -06:00
mcnc_big20.txt	Add MCNC Benchmarks netlists generation to travis regression test	2019-05-17 15:22:04 -06:00