AurelienUoU 2b04376209 Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks		2019-05-22 13:44:48 -06:00
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Blif	Add MCNC Benchmarks netlists generation to travis regression test	2019-05-17 15:22:04 -06:00
List	Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches	2019-05-21 17:24:06 -06:00
Verilog/MCNC	Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks	2019-05-22 13:44:48 -06:00