tangxifan 2f38b5cbc2 Merge branch 'refactoring' into dev		2020-03-08 16:23:20 -06:00
..
backend_assistant	bug fixed in SDC for CBs and SBs: remove useless module names	2020-01-17 15:33:50 -07:00
base	hotfix on removing dangling inputs from GSB, which are CLB direct output	2020-03-08 13:54:49 -06:00
bitstream	critical bugs fixed for routing module naming; and speed up local wire detection in Verilog writer	2019-11-08 15:01:30 -07:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
module_builder	Directlist extension bug fix	2020-03-04 09:09:06 -07:00
router	fixed bugs in configure pb_rr_graph and dependence on testbenches	2019-08-16 18:20:30 -06:00
shell	deleting legacy codes: fpga_verilog top-level function	2019-12-04 15:55:16 -07:00
spice	Rename SCFF to CCFF, configuration chain flip flop	2019-09-26 11:32:57 -06:00
verilog	hotfix on removing dangling inputs from GSB, which are CLB direct output	2020-03-08 13:54:49 -06:00