Ganesh Gore 8afcba2c45 Merge remote-tracking branch 'origin/ganesh_dev' into dev		2019-09-18 12:15:42 -06:00
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SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
arch	add tileable routing to regression test	2019-09-16 20:45:02 -06:00
benchmarks	Added Test Modes - Added blif VPR Option	2019-08-22 17:00:59 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Separated Modelsim tcl script generation	2019-09-07 12:36:22 -04:00
scripts	Added explicit checking to VVP execution	2019-09-18 12:14:26 -06:00
tasks	start refactoring the switch block verilog generation	2019-09-17 20:40:26 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00