tangxifan 89fb672631 [Tool] Fine-tune the options of 'write_simulation_task_info' to be straightforward to use		2021-06-09 10:49:00 -06:00
..
annotation	[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes	2021-04-24 14:53:29 -06:00
base	[Tool] Fine-tune the options of 'write_simulation_task_info' to be straightforward to use	2021-06-09 10:49:00 -06:00
fabric	[Tool] Change routing module port naming to include architecture port names	2021-03-14 19:35:49 -06:00
fpga_bitstream	[Tool] Now 'write_full_testbench' supports flatten(vanilla) configuration protocol	2021-06-07 21:49:31 -06:00
fpga_sdc	[Tool] Patch FPGA-SDC to consider time unit in global port timing constraints	2021-05-27 10:26:20 -06:00
fpga_spice	[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming	2020-12-05 12:44:09 -07:00
fpga_verilog	[Tool] Add a new command 'write_simulation_task_info'	2021-06-08 22:10:02 -06:00
mux_lib	[Tool] Support superLUT circuit model in core engine	2021-02-09 20:23:05 -07:00
repack	[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes	2021-04-24 14:53:29 -06:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks	2021-04-18 16:11:11 -06:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	[Tool] Add --version to openfpga shell option and a command to openfpga shell	2021-01-27 16:03:46 -07:00