AurelienUoU a2f6ded2a2 Add path modification in file changing a keyword into OpenFPGA full path		2019-06-04 15:21:15 -06:00
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Blif	Add path modification in file changing a keyword into OpenFPGA full path	2019-06-04 15:21:15 -06:00
List	Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches	2019-05-21 17:24:06 -06:00
Verilog	Add path modification in file changing a keyword into OpenFPGA full path	2019-06-04 15:21:15 -06:00