tangxifan 02fd2a69b3 [Script] Add dff with active-low async reset to default yosys tech lib		2021-07-02 11:17:43 -06:00
..
k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v	…
k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v	…
k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v	[HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks	2021-04-24 13:30:46 -06:00
k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v	[HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks	2021-04-24 13:30:46 -06:00
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt	…
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v	…
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v	…
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v	…
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v	…
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v	…
k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt	[Script] Update yosys script due to arch changes in DPRAM sizes	2021-04-28 10:55:59 -06:00
k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v	[Script] Update yosys script due to arch changes in DPRAM sizes	2021-04-28 10:55:59 -06:00
k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v	[Script] Update yosys script due to arch changes in DPRAM sizes	2021-04-28 10:55:59 -06:00
openfpga_adders_sim.v	…
openfpga_arith_map.v	…
openfpga_brams.txt	…
openfpga_brams_map.v	…
openfpga_brams_sim.v	…
openfpga_dff_map.v	[Script] Add dff with active-low async reset to default yosys tech lib	2021-07-02 11:17:43 -06:00
openfpga_dff_sim.v	[Script] Add dff with active-low async reset to default yosys tech lib	2021-07-02 11:17:43 -06:00