tangxifan 80a4872ba0 Merge pull request #222 from lnis-uofu/gg_cleanup ... [Flow] ACE is optional during flow script, only runs when power estimation is on		2021-02-08 10:08:47 -07:00
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arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file	2021-02-04 20:20:10 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	[Cleanup] Removed deadcode	2021-02-03 10:35:14 -07:00
openfpga_arch	[Arch] Decide to move external bitstream definition to a separated XML file	2021-02-01 15:57:44 -07:00
openfpga_cell_library	[HDL] Bug fix in HDL netlist due to port name mismatching	2021-02-01 11:35:25 -07:00
openfpga_shell_scripts	[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file	2021-02-04 20:20:10 -07:00
openfpga_simulation_settings	[Flow] Update simulation settings for multiple clock to allow unique clock port name	2021-01-15 10:35:43 -07:00
scripts	[Flow] ACE is optional duign flow script	2021-02-03 19:07:48 -07:00
tasks	[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file	2021-02-04 20:20:10 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	Merge pull request #217 from lnis-uofu/dev	2021-02-05 09:53:28 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00