tangxifan 9832722056 [test] now add QuickLogic memory bank to fpga bitstream regression tests		2022-05-25 11:42:32 +08:00
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dont_care_bits	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
generate_bitstream	[test] now add QuickLogic memory bank to fpga bitstream regression tests	2022-05-25 11:42:32 +08:00
load_external_architecture_bitstream/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
overload_mux_default_path/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
repack_wire_lut/config	[Test] bug fix	2021-10-30 16:50:57 -07:00
report_bitstream_distribution	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
write_io_mapping/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00