Lalit Sharma 3a855725f3 Replacing opt_rmdff with dfflegalize in yosys script		2021-04-14 05:35:05 -07:00
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formality_template.tcl	Updated formality python script	2019-09-27 14:00:57 -06:00
fpgaflow_default_tool_path.conf	Updating yosys install path	2021-04-14 05:35:05 -07:00
modelsim_proc.tcl	Added task support for modelsim script	2019-11-15 23:23:15 -07:00
modelsim_runsim.tcl	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
qlf_yosys.ys	Updating files to use the updated yosys. Also enabling yosys-plugins compilation	2021-04-14 05:35:04 -07:00
ys_tmpl_rewrite_flow.ys	[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'	2021-03-10 13:56:35 -07:00
ys_tmpl_yosys_vpr_bram_dsp_flow.ys	Replacing opt_rmdff with dfflegalize in yosys script	2021-04-14 05:35:05 -07:00
ys_tmpl_yosys_vpr_bram_flow.ys	Replacing opt_rmdff with dfflegalize in yosys script	2021-04-14 05:35:05 -07:00
ys_tmpl_yosys_vpr_dsp_flow.ys	Replacing opt_rmdff with dfflegalize in yosys script	2021-04-14 05:35:05 -07:00
ys_tmpl_yosys_vpr_flow.ys	Added fpga_flow script - Working Yosys	2019-08-09 16:49:05 -06:00
ys_tmpl_yosys_vpr_flow_with_rewrite.ys	[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'	2021-03-10 13:56:35 -07:00