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OpenFPGA/yosys/examples/intel/asicworld_lfsr
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AurelienUoU 555570c15e Update Yosys from version 0.7 to version 0.8 2019-05-23 16:03:08 -06:00
..
README Update Yosys from version 0.7 to version 0.8 2019-05-23 16:03:08 -06:00
lfsr_updown.v Update Yosys from version 0.7 to version 0.8 2019-05-23 16:03:08 -06:00
lfsr_updown_tb.v Update Yosys from version 0.7 to version 0.8 2019-05-23 16:03:08 -06:00
run_cycloneiv Update Yosys from version 0.7 to version 0.8 2019-05-23 16:03:08 -06:00
run_max10 Update Yosys from version 0.7 to version 0.8 2019-05-23 16:03:08 -06:00
runme_postsynth Update Yosys from version 0.7 to version 0.8 2019-05-23 16:03:08 -06:00
runme_presynth Update Yosys from version 0.7 to version 0.8 2019-05-23 16:03:08 -06:00

README 

Source of the files:
http://www.asic-world.com/examples/verilog/lfsr.html

Run first: runme_presynth
Generate output netlist with run_max10 or run_cycloneiv
Then, check with: runme_postsynth