OpenFPGA/yosys/examples/intel/asicworld_lfsr/runme_postsynth

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#!/bin/bash
iverilog -D POST_IMPL -o verif_post -s tb lfsr_updown_tb.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v)
vvp -N verif_post