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OpenFPGA
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OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p
History
tangxifan 3a490fdd59 bug fixing on the port map alignment 2019-08-06 14:17:56 -06:00
..
base bug fixing and get ready for testing 2019-08-06 14:17:56 -06:00
bitstream added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
clb_pin_remap cleaned unused variables 2019-05-13 14:45:02 -06:00
router added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
shell Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-13 14:45:57 -06:00
spice added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
verilog bug fixing on the port map alignment 2019-08-06 14:17:56 -06:00