tangxifan 55fbd72293 many bugs have been fixed		2019-10-30 15:50:42 -06:00
..
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	single mode is working, multi-mode is under debugging	2019-10-29 22:32:36 -06:00
arch	single mode is working, multi-mode is under debugging	2019-10-29 22:32:36 -06:00
benchmarks	add single mode test case to regression test. debugging now	2019-10-28 15:57:17 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Separated Modelsim tcl script generation	2019-09-07 12:36:22 -04:00
scripts	Added remove run directory option	2019-09-21 23:35:56 -06:00
tasks	many bugs have been fixed	2019-10-30 15:50:42 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00