27 lines
442 B
Verilog
27 lines
442 B
Verilog
module ALU(zero_flag_out,alu_out,Reg_Y_in,Bus_1_in,IR_code);
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output zero_flag_out;
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output reg [7:0]alu_out;
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input [7:0]Reg_Y_in,Bus_1_in;
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input [7:0]IR_code;
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wire [3:0]opcode=IR_code[7:4];
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always@(*)
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begin
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case(opcode)
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1: alu_out=Reg_Y_in+Bus_1_in;
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2: alu_out=Bus_1_in+~(Reg_Y_in)+1;
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3: alu_out=Reg_Y_in&(Bus_1_in);
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4: alu_out=~(Bus_1_in);
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default:alu_out=8'b0;
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endcase
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end
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assign zero_flag_out=~|alu_out;
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endmodule
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