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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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73e2b857a3
OpenFPGA
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openfpga_flow
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benchmarks
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micro_benchmark
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tangxifan
92c3449999
bug fix in the regression test due to benchmark changes
2020-07-22 13:17:05 -06:00
..
FSM_three_code
enrich micro benchmarks
2020-07-22 12:33:52 -06:00
RISC_posedge_clk
enrich micro benchmarks
2020-07-22 12:33:52 -06:00
SAPone
enrich micro benchmarks
2020-07-22 12:33:52 -06:00
and2
update microbenchmark and2 module name
2020-04-20 13:37:39 -06:00
and2_latch
update microbenchmark and2 module name
2020-04-20 13:37:39 -06:00
counter
bug fix in the regression test due to benchmark changes
2020-07-22 13:17:05 -06:00
routing_test
bug fixed in routing_test.v. Deployed to regression tests
2020-06-11 19:31:01 -06:00
test_mode_low
Added test_mode_low benchmark
2020-06-11 19:31:01 -06:00