OpenFPGA/openfpga_flow/vpr_arch
tangxifan 1d0bdcfeca [Arch] Simplify the grid layout modeling 2020-12-04 17:38:44 -07:00
..
README.md [Arch] Add tileable I/O architecture example 2020-12-04 15:59:39 -07:00
k4_N4_tileableIO_40nm.xml [Arch] Simplify the grid layout modeling 2020-12-04 17:38:44 -07:00
k4_N4_tileable_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k4_N4_tileable_GlobalTileClk_40nm.xml [Arch] Add k4 arch using global clock from tile port (with zero fc) 2020-11-10 19:17:34 -07:00
k4_N4_tileable_TileOrgzBr_40nm.xml [Arch] Add architecture for bottom-right and top-left tile organization 2020-11-04 16:24:36 -07:00
k4_N4_tileable_TileOrgzTl_40nm.xml [Arch] Add architecture for bottom-right and top-left tile organization 2020-11-04 16:24:36 -07:00
k4_N4_tileable_TileOrgzTr_40nm.xml [Arch] Add a new vpr architecture with new tile organization 2020-11-04 16:20:01 -07:00
k4_N4_tileable_full_output_crossbar_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k4_N4_tileable_no_local_routing_40nm.xml [Architecture] Bring back pin equivalence for no local routing architecture 2020-09-21 22:22:39 -06:00
k4_N5_tileable_pattern_local_routing_40nm.xml [Architecture] Add k4 series architecture using pattern-based local routing 2020-09-23 16:05:39 -06:00
k4_fracNative_N4_tileable_40nm.xml [Arch] Bug fix in nature fracturable architecture 2020-11-25 22:48:26 -07:00
k4_frac_N4_40nm.xml [Architecture] A new device layout to k4n4 to test untileable architecture 2020-09-21 18:36:50 -06:00
k4_frac_N4_tileable_40nm.xml [Architecture] Add a new device layout to k4n4 for testing tileable routing 2020-09-21 18:34:31 -06:00
k4_frac_N4_tileable_adder_chain_40nm.xml [Architecture] Add a k4n4 architecture with carry chain to quick test 2020-09-22 11:33:56 -06:00
k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml [Architecture] Add k4n4 architecture with bram block for basic tests 2020-09-22 12:22:32 -06:00
k4_frac_N4_tileable_adder_chain_mem1K_L124_40nm.xml [Architecture Add vpr architecture for k4n4 using multiple wire segments 2020-09-22 12:35:39 -06:00
k4_frac_N4_tileable_adder_chain_mem1K_frac_dsp32_40nm.xml [Architecture] Add vpr architecture for k4n4 with fracturable 32-bit multiplier 2020-09-22 15:32:11 -06:00
k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [Arch] Bug fix in caravel arch 2020-11-04 20:58:58 -07:00
k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml [Arch] Patch embedded IO architecture by forcing only 1 pad per block 2020-11-02 15:39:31 -07:00
k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [Arch] Add new architecture to test global reset ports defined thru tile ports 2020-11-30 17:43:41 -07:00
k6_N10_40nm.xml rename arch directory to be clear for its usage 2020-07-04 19:13:28 -06:00
k6_N10_tileable_40nm.xml rename arch directory to be clear for its usage 2020-07-04 19:13:28 -06:00
k6_frac_N8_tileable_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_adder_chain_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_adder_chain_mem16K_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_tileable_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_tileable_adder_chain_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml bug fix in the flagship vpr arch 2020-08-19 15:23:20 -06:00
k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_tileable_adder_register_chain_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml add fixed layouts to a flagship architecture to test bitstream generation runtime 2020-07-28 11:51:50 -06:00
k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00

README.md

Naming convention for VPR architecture files

Please reveal the following architecture features in the names to help quickly spot architecture files.

  • k<lut_size>_: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size.
    • The keyword 'frac' is to specify if fracturable LUT is used or not.
    • The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch).
  • N<le_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
  • tileable: If the routing architecture is tileable or not.
    • The keyword 'IO' specifies if the I/O tile is tileable or not
  • adder_chain: If hard adder/carry chain is used inside CLBs
  • register_chain: If shift register chain is used inside CLBs
  • scan_chain: If scan chain testing infrastructure is used inside CLBs
  • __mem<mem_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword 'wide' is to specify if the BRAM spans more than 1 column. The keyword 'frac' is to specify if the BRAM is fracturable to operate in different modes.
  • __dsp<dsp_size>: If Digital Signal Processor (DSP) is used or not. If used, the input size should be clarified here. The keyword 'wide' is to specify if the DSP spans more than 1 column. The keyword 'frac' is to specify if the DSP is fracturable to operate in different modes.
  • aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os.
  • multi_io_capacity: If I/O capacity is different on each side of FPGAs.
  • reduced_io: If I/Os only appear a certain or multiple sides of FPGAs
  • <feature_size>: The technology node which the delay numbers are extracted from.
  • TileOrgz: How tile is organized.
    • Top-left (Tl): the pins of a tile are placed on the top side and left side only
    • Top-right (Tr): the pins of a tile are placed on the top side and right side only
    • Bottom-right (Br): the pins of a tile are placed on the bottom side and right side only

Other features are used in naming should be listed here.