tangxifan 712eeb1340 bring bitstream generator for routing modules online		2020-02-23 22:09:46 -07:00
..
annotation	use constant in device annotation	2020-02-21 20:45:22 -07:00
base	start integrating fpga_bitstream. Bring data structures online	2020-02-22 23:04:42 -07:00
fabric	finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset	2020-02-20 20:26:20 -07:00
fpga_bitstream	bring bitstream generator for routing modules online	2020-02-23 22:09:46 -07:00
fpga_verilog	use constant module manager as much as possible in Verilog writer	2020-02-16 16:35:26 -07:00
mux_lib	add mux library builder	2020-02-12 14:58:23 -07:00
repack	add results saver for lb router	2020-02-22 22:10:32 -07:00
tile_direct	tile direct supports inter-column/inter-row direct connections	2020-02-15 13:42:53 -07:00
utils	use constant in device annotation	2020-02-21 20:45:22 -07:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	start working on repack	2020-02-17 17:57:43 -07:00