ganeshgore f0bed1244c Added blif file folding before VPR run		2020-01-09 16:50:34 -07:00
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SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	Adding heterogeneous synthesis requirements	2019-12-03 16:09:26 -07:00
arch	passing regression test on dpram benchmarks	2019-11-07 14:57:46 -07:00
benchmarks	passing regression test on dpram benchmarks	2019-11-07 14:57:46 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Adding heterogeneous synthesis requirements	2019-12-03 16:09:26 -07:00
scripts	Added blif file folding before VPR run	2020-01-09 16:50:34 -07:00
tasks	added duplicate_grid_pin test case	2019-12-26 15:08:31 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00