Go to file
tangxifan 704dba10e4 [ci] streamline workflow file by moving cmake commands to top-level makefile 2022-08-24 16:26:12 -07:00
.github [ci] streamline workflow file by moving cmake commands to top-level makefile 2022-08-24 16:26:12 -07:00
cmake copy missing cmake modules from vtr project 2020-01-03 21:57:19 -05:00
docker [Bugfix] dockerfile 2022-05-23 10:08:42 -06:00
docs [doc] update documentation about the activity file options 2022-08-01 21:37:22 -07:00
libs [engine] remove compile warnings 2022-08-22 20:59:50 -07:00
openfpga [script] enable IPO in cmakefile 2022-08-24 14:34:33 -07:00
openfpga_flow [script] fixed a bug on wrong path to the ace2 executable 2022-08-23 10:53:44 -07:00
vtr-verilog-to-routing@f3b5a30913 [engine] update vtr 2022-08-24 13:34:17 -07:00
yosys@dca8fb54aa [Github] Now use YosysHQ v0.10 release as a submodule 2021-10-29 14:19:26 -07:00
yosys-plugins@da931732ce Bump yosys-plugins from `ebd8fa8` to `da93173` 2022-08-16 06:22:47 +00:00
.dockerignore fixed missing yosys share directory 2021-12-02 00:05:17 -07:00
.gitignore Added binder temp files to ignore 2022-05-03 14:20:10 -06:00
.gitmodules [submodule] now use a feature branch of VTR as a submodule 2022-08-16 13:49:41 -07:00
.readthedocs.yml Support SVG in Sphinx Latex building (#220) 2021-02-07 18:53:16 -07:00
CMakeLists.txt [script] enable IPO in cmakefile 2022-08-24 14:34:33 -07:00
Dockerfile Added binder temp files to ignore 2022-05-03 14:20:10 -06:00
LICENSE Create LICENSE 2018-06-26 21:52:08 -07:00
Makefile [ci] streamline workflow file by moving cmake commands to top-level makefile 2022-08-24 16:26:12 -07:00
README.md [doc] add missing file link and show version number in frontpage README 2022-05-22 15:27:22 +08:00
VERSION.md Updated Patch Count 2022-08-17 00:02:36 +00:00
openfpga.sh [test] bug fix 2022-05-22 14:47:25 +08:00
requirements.txt [Cleanup] Removed deadcode 2021-02-03 10:35:14 -07:00

README.md

Getting Started with OpenFPGA

linux build Documentation Status Binder

Version: see VERSION.md

Introduction

The award-winning OpenFPGA framework is the first open-source FPGA IP generator supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides complete EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.

If this is your first time working with OpenFPGA, we strongly recommend you watch the introduction video about OpenFPGA

A quick overview of OpenFPGA tools can be found here. We also recommend potential users check out the summary of technical capabilities before compiling.

Compilation

A tutorial video about how to compile can be found here

Before starting, we strongly recommend you read the required dependencies at compilation guidelines. It also includes detailed information about the docker image.


Compilation Steps:

# Clone the repository and go inside it
git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA
make all

Quick Compilation Verification

To quickly verify the tool is well compiled, the user can run the following command from the OpenFPGA root directory.

source openfpga.sh
run-task compilation_verification --debug --show_thread_logs

Python3 and iVerilog v10.1+ are required. GUI will pop up if enabled during compilation.


Supported Operating Systems

We currently target OpenFPGA for:

  1. Ubuntu 18.04
  2. Red Hat 7.5

The tool was tested with these operating systems. It might work with earlier versions and other distributions.

Running with pre-built docker image

# To get the docker image from the repository, 
docker pull ghcr.io/lnis-uofu/openfpga-master:latest

# To invoke openfpga_shell
docker run -it ghcr.io/lnis-uofu/openfpga-master:latest openfpga/openfpga bash

Documentation

OpenFPGA's full documentation includes tutorials, descriptions of the design flow, and tool options.

Tutorials

You can find a set of tutorials, with which you get familiar with the tool and use OpenFPGA for various purposes.