tangxifan 6dd8d347e1 try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif		2020-06-11 19:31:01 -06:00
..
OpenFPGAShellScripts	add testcases on generate fabric/testbench only	2020-06-11 19:31:01 -06:00
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	add register chain and scan chain to Travis CI	2020-04-12 15:28:22 -06:00
arch	add arch file with spy pads	2020-04-22 12:56:09 -06:00
benchmarks	Added test_mode_low benchmark	2020-06-11 19:31:01 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
openfpga_arch	add arch file with spy pads	2020-04-22 12:56:09 -06:00
scripts	Added support for simulation setting file in the task flow	2020-06-11 19:28:13 -06:00
tasks	try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif	2020-06-11 19:31:01 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00