26 lines
406 B
Verilog
26 lines
406 B
Verilog
///////////////////////////////////////////
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// Functionality: Counter with asynchronous reset
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// Author: Xifan Tang
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////////////////////////////////////////
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module counter (
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clk,
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reset,
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result
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);
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input clk;
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input reset;
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output [7:0] result;
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reg [7:0] result;
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always @(posedge clk or posedge reset)
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begin
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if (reset)
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result = 0;
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else
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result = result + 1;
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end
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endmodule
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