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behavioral_verilog/config
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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benchmark_sweep
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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bram
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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compilation_verification/config
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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depopulate_crossbar/config
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add depopulate crossbar test case
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2020-07-24 18:06:02 -06:00 |
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duplicated_grid_pin/config
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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fabric_chain
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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fabric_key
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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fixed_simulation_settings/config
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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flatten_routing/config
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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full_testbench
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bug fix in the testcases using yosys_vpr flow
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2020-07-22 12:44:19 -06:00 |
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generate_bitstream/config
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bug fix in the testcases using yosys_vpr flow
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2020-07-22 12:44:19 -06:00 |
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generate_fabric/config
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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generate_spice/config
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add test case for FPGA-SPICE
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2020-07-24 19:12:35 -06:00 |
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generate_testbench/config
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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hard_adder/config
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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implicit_verilog/config
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bug fix in the regression test due to benchmark changes
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2020-07-22 13:17:05 -06:00 |
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io
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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lut_design
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use k6_n10 architecture to reduce CI runtime
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2020-07-22 13:45:55 -06:00 |
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mcnc_big20/config
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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mux_design
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use k6 n10 in mux designs to speed up CI
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2020-07-22 13:54:09 -06:00 |
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ncounter/config
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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power_gated_design/power_gated_inverter/config
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add power gate inverter test case (full testbench)
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2020-07-22 20:09:52 -06:00 |
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preconfig_testbench
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bug fix in the testcases using yosys_vpr flow
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2020-07-22 12:44:19 -06:00 |
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sdc_time_unit/config
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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spypad/config
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fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
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2020-07-15 17:52:41 -06:00 |
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untileable/config
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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.gitignore
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Added gitignore to skip run directory tracking
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2019-08-19 19:06:01 -06:00 |
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generate_testbenches
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Reorganize task directory
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2020-07-04 19:06:41 -06:00 |
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