AurelienUoU 09fd2afa9c Adding heterogeneous synthesis requirements		2019-12-03 16:09:26 -07:00
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adder.v	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
dpram.v	Adding heterogeneous synthesis requirements	2019-12-03 16:09:26 -07:00
dpram_tb.v	Adding DPRAM behavioural Verilog netlist and its TB	2019-12-03 13:58:20 -07:00
ff.v	use prefix instead of lib_name when building modules, then use lib_name for standard cell modules	2019-11-05 15:41:59 -07:00
ff_tb.v	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
io.v	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
lb_tb.v	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
lut6.v	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
mux2.v	bug fixed for std cell MUX2 architecture and add the case to regression tests	2019-11-06 16:06:47 -07:00
mux_tb.v	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
sram.v	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
sram_tb.v	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00