OpenFPGA/fpga_flow/benchmarks/Verilog/MCNC
AurelienUoU b4c97f86a3 Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00
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alu4 Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
apex2 Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
apex4 Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
bigkey Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00
clma Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00
des Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
diffeq Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00
dsip Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00
elliptic Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00
ex5p Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
ex1010 Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
frisc Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00
misex3 Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
pdc Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
s298 Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00
s38417 Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00
s38584 Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00
seq Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
spla Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
tseng Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00