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OpenFPGA/fpga_flow/benchmarks/Verilog
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AurelienUoU b4c97f86a3 Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00
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MCNC Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00