Tarachand Pagarani 31f47a44af add example of setting bistream for hard logic block from eblif		2021-12-14 07:05:15 -08:00
..
formality_template.tcl	Updated formality python script	2019-09-27 14:00:57 -06:00
fpgaflow_default_tool_path.conf	add plugins, set yosys install for plugin	2021-11-04 07:22:09 +05:30
modelsim_proc.tcl	Added task support for modelsim script	2019-11-15 23:23:15 -07:00
modelsim_runsim.tcl	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
qlf_yosys.ys	Updating yosys-plugin compilation to create command synth_ql instead of synth_quicklogic. This is done to surpass the assertion failure	2021-11-12 01:46:06 -08:00
ys_tmpl_rewrite_flow.ys	[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'	2021-03-10 13:56:35 -07:00
ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys	[Flow] bug fix	2021-10-30 16:09:31 -07:00
ys_tmpl_yosys_vpr_bram_dsp_flow.ys	[Flow] bug fix	2021-10-30 16:52:32 -07:00
ys_tmpl_yosys_vpr_bram_flow.ys	[Flow] Add comments to clarify the limitations	2021-10-30 19:17:11 -07:00
ys_tmpl_yosys_vpr_dff_flow.ys	[Flow] Enable flatten for dff-related yosys scripts	2021-10-30 15:12:34 -07:00
ys_tmpl_yosys_vpr_dsp_flow.ys	add example of setting bistream for hard logic block from eblif	2021-12-14 07:05:15 -08:00
ys_tmpl_yosys_vpr_flow.ys	[Flow] Enable flatten for dff-related yosys scripts	2021-10-30 15:12:34 -07:00
ys_tmpl_yosys_vpr_flow_with_rewrite.ys	add example of setting bistream for hard logic block from eblif	2021-12-14 07:05:15 -08:00