OpenFPGA/vpr7_x2p/vpr/ARCH
tangxifan 4b852afeac skip rotating mirror detection which is too time-consuming 2019-05-25 23:41:46 -06:00
..
.regression_k6_N10_sram_chain_HC.xml Verilog verification with Travis 2019-05-15 15:57:05 -06:00
.travis_k6_N10_sram_chain_HC.xml Add travis full path to avoid missing sources 2019-05-16 15:51:10 -06:00
k6_N10_sram_chain_HC_template.xml skip rotating mirror detection which is too time-consuming 2019-05-25 23:41:46 -06:00