AurelienUoU b4c97f86a3 Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches		2019-05-21 17:24:06 -06:00
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arch/fpga_spice	Bug fix in Icarus requirement	2019-05-10 14:07:32 -06:00
benchmarks	Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches	2019-05-21 17:24:06 -06:00
configs	update file organization and be ready for SB/CB class	2019-05-21 12:15:38 -06:00
scripts	Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches	2019-05-21 17:24:06 -06:00
tech	Add the PTM to the benchmark flow	2018-11-21 11:32:34 -07:00
vpr_fpga_spice_conf	Reorganize the code directory	2018-07-26 11:28:21 -06:00
regression_fpga_flow.sh	Update flow and allow netlist generation	2019-05-17 17:00:38 -06:00
run_fpga_spice_testbench_study.sh	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00