OpenFPGA/vpr7_x2p/vpr/SRC/device/rr_graph
tangxifan 1332ba62e8 update tileable rr_graph generator to improve routability and also enable assoicated testing 2019-06-27 17:52:25 -06:00
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chan_node_details.cpp bug fixing for tileable rr_graph generator. 2019-06-22 20:41:06 -06:00
chan_node_details.h many bug fixing for tileable rr_graph generator. Still debugging 2019-06-21 17:58:46 -06:00
gsb_graph.cpp start building object GSB graph 2019-06-17 22:10:30 -06:00
gsb_graph.h start building object GSB graph 2019-06-17 22:10:30 -06:00
rr_graph_builder_utils.cpp minor fixing in printing the rr_node stats 2019-06-27 16:34:21 -06:00
rr_graph_builder_utils.h minor fixing in printing the rr_node stats 2019-06-27 16:34:21 -06:00
rr_graph_fwd.h fixed a bug in Verilog generator supporting SRAM5T 2019-06-13 14:42:39 -06:00
tileable_chan_details_builder.cpp many bug fixing and now start improving the routability of tileable rr_graph 2019-06-24 17:33:29 -06:00
tileable_chan_details_builder.h bug fixing and reorganize rr_graph builder source files 2019-06-23 16:40:13 -06:00
tileable_rr_graph_builder.cpp minor fixing in printing the rr_node stats 2019-06-27 16:34:21 -06:00
tileable_rr_graph_builder.h bug fixing and reorganize rr_graph builder source files 2019-06-23 16:40:13 -06:00
tileable_rr_graph_gsb.cpp update tileable rr_graph generator to improve routability and also enable assoicated testing 2019-06-27 17:52:25 -06:00
tileable_rr_graph_gsb.h bug fixing and reorganize rr_graph builder source files 2019-06-23 16:40:13 -06:00