OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p
tangxifan 4398cffaaa single mode is working, multi-mode is under debugging 2019-10-29 22:32:36 -06:00
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base single mode is working, multi-mode is under debugging 2019-10-29 22:32:36 -06:00
bitstream single mode is working, multi-mode is under debugging 2019-10-29 22:32:36 -06:00
clb_pin_remap cleaned unused variables 2019-05-13 14:45:02 -06:00
module_builder single mode is working, multi-mode is under debugging 2019-10-29 22:32:36 -06:00
router fixed bugs in configure pb_rr_graph and dependence on testbenches 2019-08-16 18:20:30 -06:00
shell added Verilog generation for preconfig top module 2019-10-29 13:54:35 -06:00
spice Rename SCFF to CCFF, configuration chain flip flop 2019-09-26 11:32:57 -06:00
verilog single mode is working, multi-mode is under debugging 2019-10-29 22:32:36 -06:00