OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream
tangxifan 4398cffaaa single mode is working, multi-mode is under debugging 2019-10-29 22:32:36 -06:00
..
bitstream_writer.cpp fixed bugs in refactored bitstream generation 2019-10-26 16:40:14 -06:00
bitstream_writer.h add bitstream writers and start debugging 2019-10-26 12:41:23 -06:00
build_device_bitstream.cpp added fabric bitstream generator and fixed critical bugs in top module graph 2019-10-27 18:47:33 -06:00
build_device_bitstream.h start refactoring bitstream generator 2019-10-24 21:01:11 -06:00
build_fabric_bitstream.cpp added fabric bitstream generator and fixed critical bugs in top module graph 2019-10-27 18:47:33 -06:00
build_fabric_bitstream.h added fabric bitstream generator and fixed critical bugs in top module graph 2019-10-27 18:47:33 -06:00
build_grid_bitstream.cpp add instance name for each pb graph node 2019-10-26 17:25:45 -06:00
build_grid_bitstream.h refactored grid bitstream generation 2019-10-25 21:49:47 -06:00
build_lut_bitstream.cpp single mode is working, multi-mode is under debugging 2019-10-29 22:32:36 -06:00
build_lut_bitstream.h refactored grid bitstream generation 2019-10-25 21:49:47 -06:00
build_mux_bitstream.cpp fixed bugs in refactored bitstream generation 2019-10-26 16:40:14 -06:00
build_mux_bitstream.h start refactoring bitstream generator 2019-10-24 21:01:11 -06:00
build_routing_bitstream.cpp added fabric bitstream generator and fixed critical bugs in top module graph 2019-10-27 18:47:33 -06:00
build_routing_bitstream.h added fabric bitstream generator and fixed critical bugs in top module graph 2019-10-27 18:47:33 -06:00
fpga_bitstream.c add bitstream writers and start debugging 2019-10-26 12:41:23 -06:00
fpga_bitstream.h start refactoring the bitstream part using spice_models 2019-08-16 15:58:14 -06:00
fpga_bitstream_pbtypes.c added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
fpga_bitstream_pbtypes.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
fpga_bitstream_primitives.c Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
fpga_bitstream_primitives.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
fpga_bitstream_routing.c replace spice_models with circuit model in bitstream generator 2019-08-16 16:36:49 -06:00
fpga_bitstream_routing.h replace spice_models with circuit model in bitstream generator 2019-08-16 16:36:49 -06:00