tangxifan 59f1ac7310 add missing files and try to refactor submodule essential		2019-08-20 20:49:26 -06:00
..
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
arch	Added architecture and replaced variables	2019-08-19 19:02:50 -06:00
benchmarks/MCNC_Verilog	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Removed unused templates and file from openfpga_flow directory	2019-08-19 21:32:52 -06:00
scripts	Removed traces of old template file	2019-08-20 15:58:19 -06:00
tasks	add missing files and try to refactor submodule essential	2019-08-20 20:49:26 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00