AurelienUoU cc5a01d476 Fix waveform generation + add benchmark and update go.sh		2018-12-11 22:21:39 -07:00
..
base	update blif reader to identify clock signals	2018-12-10 13:28:44 -07:00
clb_pin_remap	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
spice	fix bugs for wired LUTs	2018-11-27 12:46:30 -07:00
verilog	Fix waveform generation + add benchmark and update go.sh	2018-12-11 22:21:39 -07:00