tangxifan 3cf7950bc1 add wire module generation and simplify Verilog generation for wires		2019-10-21 20:20:34 -06:00
..
base	add const 0 and 1 module Verilog generation	2019-10-21 14:17:09 -06:00
bitstream	replace spice_models with circuit model in bitstream generator	2019-08-16 16:36:49 -06:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
module_builder	add wire module generation and simplify Verilog generation for wires	2019-10-21 20:20:34 -06:00
router	fixed bugs in configure pb_rr_graph and dependence on testbenches	2019-08-16 18:20:30 -06:00
shell	move mux_lib to fpga_x2p_setup	2019-10-19 19:13:52 -06:00
spice	Rename SCFF to CCFF, configuration chain flip flop	2019-09-26 11:32:57 -06:00
verilog	add wire module generation and simplify Verilog generation for wires	2019-10-21 20:20:34 -06:00