Go to file
Lalit Sharma 3a82bae1ac Updating compilation steps 2020-12-11 03:51:23 -08:00
.github Adding tcl8.6-dev package as CI dependency 2020-12-08 21:14:48 -08:00
.travis [Test] Now travis and github actions share the common regression test scripts 2020-11-24 15:58:09 -07:00
abc Add latest abc and update ace dependence 2019-05-03 18:56:03 -06:00
ace2 Now we use the ace from VTR 2019-07-16 17:00:09 -06:00
cmake copy missing cmake modules from vtr project 2020-01-03 21:57:19 -05:00
docs [Doc] Typo fix 2020-12-04 15:07:02 -07:00
libopenfpga [Tool] Bug fix in XML syntax to define default values for a global tile port 2020-12-02 17:03:48 -07:00
libs bug fixing to constant string to display interconnect names 2020-04-07 18:28:19 -06:00
openfpga [Tool] Avoid outputting signal initialization codes because they are bulky 2020-12-06 14:29:16 -07:00
openfpga_flow [Arch] Bug fix in tileable I/O arch example 2020-12-04 17:56:54 -07:00
vpr [Tool] Tileable rr_graph now accept I/Os in center grid 2020-12-04 17:43:35 -07:00
yosys@9ac3484a18 Updating yosys branch to quicklogic-rebased 2020-12-09 23:36:13 -08:00
.dockerignore Added dockerignore + minor changes in openfpga_flow script 2019-08-17 16:22:52 -06:00
.gitignore modify the git ignore list for ctags so that we only ignore those tags in specific folders 2020-01-03 21:17:40 -07:00
.gitmodules Removing yosys-symbiflow-plugins submodule and will be added separately later via another PR 2020-12-10 21:06:08 -08:00
.readthedocs.yml [Doc] Add readthedoc setting file 2020-11-12 19:43:43 -07:00
.travis.yml [Regression Tests] Add gcc-5 compatibility test to Travis CI 2020-09-14 20:14:16 -06:00
CMakeLists.txt Removing yosys-symbiflow-plugins compilation from CMakefile 2020-12-10 21:44:57 -08:00
Dockerfile [Documentation] Use release mode in Docker settings 2020-09-20 15:00:56 -06:00
LICENSE Create LICENSE 2018-06-26 21:52:08 -07:00
Makefile Adding updates to checkout submodules 2020-12-08 08:52:35 -08:00
README.md Updating compilation steps 2020-12-11 03:51:23 -08:00
deploy_key.enc Updated Encrypt Key 2019-11-02 16:37:00 -06:00
openfpga.sh Script cleanup 2020-09-23 14:06:33 -06:00
run_local.bat Working lattice benchmark unclean commit 2019-08-08 18:08:39 -06:00
run_local.sh Added build files in .gitignore 2019-08-17 22:59:54 -06:00

README.md

Getting Started with OpenFPGA

linux build Documentation Status

Introduction

The award-winning OpenFPGA framework is the first open-source FPGA IP generator supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.

A quick overview of OpenFPGA tools can be found here. We also recommend potential users to checkout the summary of technical capabilities before compiling.

Compilation

Before start, we strongly recommend you to read the required dependencies at compilation guidelines. It also includes detailed information about docker image.


Compilation Steps:

# Clone the repository and go inside it
git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA
make all

Quick Compilation Verification

To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository.

python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug --show_thread_logs

Python3 and iVerilog v10.1+ are required. GUI will pop-up if enabled during compilation.


Supported Operating Systems

We currently target OpenFPGA for:

  1. Ubuntu 18.04
  2. Red Hat 7.5

The tool was tested with these operating systems. It might work with earlier versions and other distributions.

Documentation

OpenFPGA's full documentation includes tutorials, descriptions of the design flow, and tool options.

Tutorials

You can find some tutorials in the ./tutorials folder. This will help you get more familiar with the tool and use OpenFPGA under different configurations.