tangxifan b6bdf78d95 bug fixed for heterogeneous block instances in top module		2020-03-24 17:39:26 -06:00
..
and_k6_frac.openfpga	add a microbenchmark `and_latch` to test LUTs in wired mode	2020-03-11 10:40:59 -06:00
and_k6_frac_adder_chain.openfpga	fix bugs in flow manager on default compress routing problems	2020-03-22 15:26:15 -06:00
and_k6_frac_adder_chain_mem16K.openfpga	bug fixed for heterogeneous block instances in top module	2020-03-24 17:39:26 -06:00
and_latch_k6_frac.openfpga	debugging multi-source lb router	2020-03-12 20:42:41 -06:00