tangxifan e0d7bcfa11 [Tool] Bug fix for region-based fabric bitstream using memory bank and frame-based protocols		2020-09-29 12:49:32 -06:00
..
annotation	[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker	2020-09-02 22:16:10 -06:00
base	[OpenFPGA Tool] Bug fix for long runtime	2020-09-28 20:42:18 -06:00
fabric	[OpenFPGA Tool] Bug fix for long runtime	2020-09-28 20:42:18 -06:00
fpga_bitstream	[Tool] Bug fix for region-based fabric bitstream using memory bank and frame-based protocols	2020-09-29 12:49:32 -06:00
fpga_sdc	hotfix on treating the dangling ports in pb_graph for analysis SDC generator	2020-07-09 23:28:42 -06:00
fpga_spice	[FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation	2020-09-20 15:21:33 -06:00
fpga_verilog	[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches	2020-09-29 12:22:10 -06:00
mux_lib	bug fix in lut and mux module generation on supporting spypads	2020-04-22 14:41:16 -06:00
repack	[OpenFPGA Tool] Bug fix for repacking no local routing architecture	2020-09-21 22:22:03 -06:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches	2020-09-29 12:22:10 -06:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	start transplanting FPGA-SPICE	2020-07-05 12:10:12 -06:00