AurelienUoU b810b5cab9 fpga_flow bug fix + upload k8 architecture		2019-07-16 07:04:45 -06:00
..
ARCH	Removed all local files	2019-07-03 14:26:06 -06:00
Circuits	Add missing Verilog source, Archictecture folder and Testbenches correction	2019-05-13 16:41:35 -06:00
SRC	Merge branch 'dev' into documentation	2019-07-15 21:19:26 -06:00
SpiceNetlists	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
VerilogNetlists	Regression test succeeded	2019-07-09 09:18:06 -06:00
CMakeLists.txt	fix CMakeList bug in disabling VPR graphics	2019-06-15 13:21:25 -06:00
go_fpga_spice.sh	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
go_fpga_verilog.sh	rename rr_switch_block to rr_gsb, a generic block	2019-06-06 17:41:01 -06:00
go_ganesh.sh	Added additional architecure files	2019-06-11 11:26:44 -06:00
regression_verilog.sh	fpga_flow bug fix + upload k8 architecture	2019-07-16 07:04:45 -06:00