OpenFPGA/openfpga_flow/scripts
Lalit Sharma 6a1ce01084 Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS 2021-03-07 22:02:11 -08:00
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pro_blif.pl now pro_blif.pl can accept customized clock name 2020-08-19 09:43:44 -06:00
run_formality.py Updated formality python script 2019-09-27 14:00:57 -06:00
run_fpga_flow.py Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS 2021-03-07 22:02:11 -08:00
run_fpga_task.conf Updated to run with python3 2019-08-31 21:42:31 -06:00
run_fpga_task.py Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family 2021-03-04 01:10:47 -08:00
run_modelsim.py BugFix : Relative path for refrence benchmark fixed 2020-04-25 20:16:17 -06:00