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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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2bd8ef2af9
OpenFPGA
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openfpga_flow
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tangxifan
e1f8b252b1
Merge branch 'master' into yosys_heterogeneous_block_support
2021-03-16 20:05:21 -06:00
..
pro_blif.pl
now pro_blif.pl can accept customized clock name
2020-08-19 09:43:44 -06:00
run_formality.py
Updated formality python script
2019-09-27 14:00:57 -06:00
run_fpga_flow.py
Merge branch 'master' into yosys_heterogeneous_block_support
2021-03-16 20:05:21 -06:00
run_fpga_task.conf
Updated to run with python3
2019-08-31 21:42:31 -06:00
run_fpga_task.py
[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr
2021-03-10 13:36:11 -07:00
run_modelsim.py
BugFix : Relative path for refrence benchmark fixed
2020-04-25 20:16:17 -06:00