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OpenFPGA/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb
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tangxifan 0a0d10b36d [HDL] Bug fix in Verilog syntax 2021-06-22 16:18:46 -06:00
..
counter.v [HDL] Bug fix in Verilog syntax 2021-06-22 16:18:46 -06:00
counter_tb.v [HDL] Add more micro benchmarks for counter, and-gate and mac unit 2021-06-21 16:48:35 -06:00