OpenFPGA/openfpga_flow
tangxifan 22e675148e [HDL] Add HDL codes for a super LUT with embedded carry logic 2021-02-09 21:13:22 -07:00
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arch_bitstreams [Architecture] Update external bitstream 2020-09-25 21:30:59 -06:00
benchmarks [Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture 2021-02-09 15:41:21 -07:00
docs Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00
fabric_keys [Architecture] Add example fabric key using multiple regions 2020-09-29 14:14:50 -06:00
misc [Cleanup] Removed deadcode 2021-02-03 10:35:14 -07:00
openfpga_arch [Arch] Patch architecture to support superLUT-related XML syntax 2021-02-09 20:23:32 -07:00
openfpga_cell_library [HDL] Add HDL codes for a super LUT with embedded carry logic 2021-02-09 21:13:22 -07:00
openfpga_shell_scripts [Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file 2021-02-04 20:20:10 -07:00
openfpga_simulation_settings [Flow] Update simulation settings for multiple clock to allow unique clock port name 2021-01-15 10:35:43 -07:00
scripts [Cleanup] Removed deadcode 2021-02-03 10:35:14 -07:00
tasks [Test] Update test case to use dedicated eblif file 2021-02-09 15:51:57 -07:00
tech Added Power Model Files 2019-08-19 18:55:23 -06:00
vpr_arch [Arch] Bug fix in the example arch with super LUT 2021-02-09 15:52:22 -07:00
.gitignore Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00